1. Field of the Invention
The present invention generally relates to methods and structures for distributing clock signals within a semiconductor processor environment and, more particularly, to a methodology for growing and inserting clock trees on high-performance, low power application specific integrated circuit (ASIC) chips.
2. Description of the Related Art
Balanced clock distribution networks have historically fallen into four categories--meshes or grids, "H" or "I" trees, spines, and distributed buffers with or without balanced wiring. For example, FIG. 1(a) illustrates an "H" tree, FIG. 1(b) illustrates a spine structure and FIG. 1(c) illustrates a mesh layout.
Mesh or grid methods are often simple to lay out, but have greater amounts of wire and higher capacitance than is necessary, which increases power requirements and reduces wireability. This problem is compounded when multiple clock domains are required, which is very common in a large variety of ASICs.
The "H" or "I" trees tend to have wide wires at their roots. Such wide wires are more susceptible to inductance at high frequency, which limits the latency or performance of the clock distribution network.
Conventional "H" trees are often driven from a localized source, causing noise or power supply dips. Often, a special analysis must be performed or the power buses must be strengthened in those regions to eliminate the noise or power supply dips. These steps can delay design schedules and limit floor plan changes.
Electromigration problems are also aggravated by localized wiring and sources. Pure "H" or "I" trees can also add more wire than is necessary.
Additionally, spines, or fishbones, have resistance/capacitance (RC) drops across them, which causes undesirable clock skew. Distributed buffers (with or without balanced routing) suffer from process variations and added latency, increasing skew and decreasing performance.
Further, inductance effects often go unnoticed in narrow single wires because the resistance is much greater than the inductive-reactance term. For clock networks, however, wide wires are often used to reduce resistance. If the transition time is fast enough (as is typically required at higher frequencies), the inductive-reactance term becomes significant with respect to the resistance. If this inductance is not considered, large errors in delays can result.
The following table shows the delay measured across a 10 mm wire segment with a 200 ps transition time input to the circuit. The delay is modeled, first without using inductance and then including inductance effects. The results presented in the following table show that the wire can be as much as 130 ps slower when inductance is considered.
Wire Width (.mu.m) RC Delay (ps) RLC Delay (ps) Difference (ps) 0.9 406.0 406.0 0 50 206.3 336.0 130
The difference in latency can result in skew if wide wires are used on some networks and narrow wires are used on other networks. Wide wires can have additional delay differences if return paths are not modeled correctly.